1. Field of the Invention
The present invention relates to a process for producing a semiconductor device which has an interlayer insulating film of low dielectric constant and interconnects of low resistance and which is operable at a high speed.
2. Description of the Prior Art
Conventional processes for production of semiconductor device include, for example, a process described in Japanese Patent Application Laid-Open No. 196870/1987. This process comprises (1) a step of forming a gate electrode, etc. on a semiconductor substrate, (2) a step of forming thereon an interlayer insulating film, (3) a step of conducting a high-temperature in-N.sub.2 heat treatment, (4) a step of forming contact holes in the interlayer insulating film, (5) a step of conducting a high-temperature (450.degree. C. or higher) in-H.sub.2 heat treatment, (6) a step of forming an aluminum interconnect, and (7) a step of conducting a low-temperature in-N.sub.2 heat treatment. In this process, since the heat treatments (3) and (5) are conducted before the formation of an aluminum interconnect, insufficient contact at the interface between the aluminum interconnect and Si can be prevented and further the surface state such as cause d by the dangling bond of Si can be eliminated.
As processes for production of semiconductor device which comprise a step of growing a metal only in the contact holes by selective chemical vapor deposition, there is, for example, a process described in Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, Makuhari, 1993, pp. 180-182. In this process, contact holes are formed in an interlayer insulating film composed of SiO.sub.2 ; in each hole is formed an aluminum plug by chemical vapor deposition using Al(CH.sub.3).sub.2 H; then, an aluminum film is deposited on the whole surface of the resulting substrate by sputtering. According to this process, there is obtained a structure as shown in FIG. 3, comprising a Si substrate 31, a first SiO.sub.2 film 32, a lower aluminum interconnect 33, a second SiO.sub.2 film 34 and an upper aluminum interconnect 35, wherein the lower aluminum interconnect 33 and the upper aluminum interconnect 35 are connected with each other via Al plugs 36. This process can provide interconnects of low resistance.
For formation of a wiring when an insulating film of 3.5 or lower dielectric constant is used, there is, for example, a process described in 43rd-OYOUBUTURIGAKUKANKEIRENGO KOENKAIYOKOSYU No. 2, p751, 27p-Q-14. In this process, as shown in FIG. 4, a groove is formed in a BCB (benzocyclobutene) film 42 provided on a Si substrate 41, and a Cu wiring 43 is formed in the groove.
The above-mentioned prior art, however, has had the following problems.
In the process described in Japanese Patent Application Laid-Open No. 196870/1987, since it is necessary to eliminate, by the low-temperature in-N.sub.2 heat treatment step (7) after formation of an aluminum interconnect, the hydrogen of low bonding force from the interface between the gate electrode and the interlayer insulating film and also from the interface between the substrate and the interlayer insulating film, the heat treatment temperature of the step (7) is as high as at least about 400.degree. C. Therefore, in the process, it is impossible to use, as the interlayer insulating film, an organic film of low heat resistance, and accordingly it is impossible to allow the interlayer insulating film to have a low dielectric constant and no LSI of high-speed operation is obtainable.
In the process shown in FIG. 3, since a SiO.sub.2 film is used as the interlayer insulating film, the dielectric constant of the film is as high as at least 4 and no LSI of high-speed operation is obtainable.
In the process shown in FIG. 4, since only one layer of wiring is formed, electrical connection between upper and lower wirings is difficult when a multi-layered structure is obtained. Therefore, the process is generally inapplicable in production of a high-speed LSI using multi-level wirings.